An A/D converter (analog/digital converter: Analog to Digital converter: hereinafter, also referred to as an ADC) samples a voltage of an input analog signal, and converts to a digital code corresponding to a magnitude of the input analog voltage (voltage of the input signal).
A successive approximation A/D converter (successive approximation type analog/digital converter: Successive Approximation ADC: hereinafter, also referred to as an SAR-ADC), which is a form of the ADC, includes high compatibility with CMOS processes and may be manufactured at relatively low cost.
Further, the SAR-ADC may achieve a relatively fast conversion time, for example, in a recent miniaturized manufacturing process and 8-bit to 12-bit resolution, may achieve in a speed of about several tens to several hundred mega samples/sec.
Incidentally, the SAR-ADC is, for example, built-in a Micro-Controller Unit (MCU) or widely applied to various semiconductor integrated circuits including a digital TV demodulation IC (Integrated Circuit).
Here, the SAR-ADC includes, for example, an internal D/A converter (digital/analog converter: Digital to Analog Converter: hereinafter, also referred to as a DAC), a comparator, and a control circuit for controlling them.
Such an SAR-ADC compares an input signal voltage with a voltage generated by the internal D/A converter in many times, and determines (obtains) a digital code corresponding to the input signal voltage, wherein the determining of the comparator may be generally performed by using a binary search.
As described above, the SAR-ADC generally converts an input signal voltage into a digital code by comparing and determining a relationship between a voltage generated by the internal D/A converter and the input signal voltage in many times based on the binary search.
Conventionally, regarding an A/D converter, in a region where a high-speed A/D conversion is required, a pipeline ADC is generally applied. However, in accordance with miniaturization of manufacturing process, a power supply voltage is reduced to 1 Volt or lower, and now, a high gain amplifier, which is used as a major component of the pipeline ADC, may become difficult to realize.
At present, an SAR-ADC has been widely applied in accordance with the above circumstances. Specifically, in the SAR-ADC, the high gain amplifier is not necessary, and further, power efficiency may be improved in accordance with the miniaturization of the manufacturing process.
As described above, in accordance with the miniaturization of the manufacturing process, an SAR-ADC may become possible to operate at a high speed. Nevertheless, a problem where an operation speed of the ADC is limited by a bandwidth of a package may be caused.
For example, the performance of the device (SAR-ADC) is improved in accordance with the miniaturization of the manufacturing process, but a size of a semiconductor integrated circuit (IC package) applying the device is not sufficiently reduced.
Specifically, in a 12-bit SAR-ADC, for example, at least 12 times of determination processes may be necessary to obtain a 12-bit result (digital codes) by using a binary search. Further, in the case of requesting some cycles in addition to cycles for directly determining the digital code, for example, 20 clock cycles may be necessary to obtain the 12-bit result.
Therefore, for example, in order to achieve 50 MSPS by using an SAR-ADC which requires 20 clock cycles for one conversion time, the clock frequency may be set to 1 GHz, i.e., a clock cycle time may be set to 1 ns. This means that the reference voltage supplied via the IC packages may be converged within 1 ns.
However, in the case of a typical low-cost IC package, a parasitic inductance of approximately 6 nH per pin may be present. Therefore, it is difficult to converge the reference voltage within 1 ns.
Here, the above matter may cause a decision error of comparing the input signal voltage with the voltage generated by the internal DAC (output of the internal DAC). Further, for example, when a decision error is caused in a prescribed bit by the comparator, it is difficult to correct (compensate) subsequent low-order bits of the prescribed bit.
As described above, in the conventional SAR-ADC (A/D converter), various problems to be solved may be present, and therefore, for example, it is required to realize a low voltage and a high-speed operation, and compensate a decision error caused by comparing an input signal voltage with an output of the internal DAC.
A various successive approximation A/D converter applied to a semiconductor integrated circuit has conventionally been proposed.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2014-042358    Patent Document 2: Japanese National Publication of International Patent Application No. 2010-519810    Patent Document 3: Japanese Laid-Open Patent Publication No. 2003-283336    Patent Document 4: Japanese Laid-Open Patent Publication No. 2004-032089    Patent Document 5: Japanese Laid-Open Patent Publication No. 2004-080075    Patent Document 6: U.S. Pat. No. 5,870,052    Patent Document 7: International Publication Pamphlet No. WO 2012/157155    Patent Document 8: Japanese Laid-Open Patent Publication No. 2011-205230    Patent Document 9: Japanese Laid-Open Patent Publication No. H02(1990)-024898    Non-Patent Document 1: F. KUTTNER, “A 1.2V 10b 20M Sample/s Non-Binary Successive Approximation ADC in 0.13 μm CMOS”, ISSCC Digest of Technical Papers, 10.6, February 2002.    Non-Patent Document 2: Chun-Cheng Liu et al., “A 10b 100 MS/s 1.13 mW SAR ADC with Binary-Scaled Error Compensation”, ISSCC Digest of Technical Papers, 21.5, pp. 386-387, February 2010.    Non-Patent Document 3: Chun-Cheng Liu et al., “A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 μm CMOS Process”, Symposium on VLSI Circuits Digest of Technical Papers, 23-1, pp. 236-237, June 2009.